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	<title>Grupo InDeA. VHDL - FPGA. UTN - FRM.</title>
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	<description>Grupo de I+D dedicado al uso de VHDL sobre FPGA</description>
	<lastBuildDate>Thu, 13 Mar 2008 13:32:03 +0000</lastBuildDate>
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		<title>Grupo InDeA. VHDL - FPGA. UTN - FRM.</title>
		<link>http://utnvhdl.wordpress.com</link>
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		<item>
		<title>Spartan-3A/3AN FPGA Starter Kit Board Design Examples</title>
		<link>http://utnvhdl.wordpress.com/2008/03/13/spartan-3a3an-fpga-starter-kit-board-design-examples/</link>
		<comments>http://utnvhdl.wordpress.com/2008/03/13/spartan-3a3an-fpga-starter-kit-board-design-examples/#comments</comments>
		<pubDate>Thu, 13 Mar 2008 13:32:03 +0000</pubDate>
		<dc:creator>Rodrigo G.</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[VHDL]]></category>

		<guid isPermaLink="false">http://utnvhdl.wordpress.com/2008/03/13/spartan-3a3an-fpga-starter-kit-board-design-examples/</guid>
		<description><![CDATA[Example designs created for the Spartan™-3A FPGA Starter Kit board and the Spartan-3AN FPGA Starter Kit board to demonstrate various features or capabilities.  Documentation and source files are included. http://www.xilinx.com/products/boards/s3astarter/reference_designs.htm <img alt="" border="0" src="http://stats.wordpress.com/b.gif?host=utnvhdl.wordpress.com&amp;blog=1756929&amp;post=14&amp;subd=utnvhdl&amp;ref=&amp;feed=1" width="1" height="1" />]]></description>
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		<slash:comments>1</slash:comments>
	
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			<media:title type="html">Rodrigo G.</media:title>
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	</item>
		<item>
		<title>Evita™ HDL Tutorials</title>
		<link>http://utnvhdl.wordpress.com/2008/03/12/evita%e2%84%a2-hdl-tutorials/</link>
		<comments>http://utnvhdl.wordpress.com/2008/03/12/evita%e2%84%a2-hdl-tutorials/#comments</comments>
		<pubDate>Wed, 12 Mar 2008 22:31:52 +0000</pubDate>
		<dc:creator>Rodrigo G.</dc:creator>
				<category><![CDATA[UTN]]></category>
		<category><![CDATA[VHDL]]></category>

		<guid isPermaLink="false">http://utnvhdl.wordpress.com/2008/03/12/evita%e2%84%a2-hdl-tutorials/</guid>
		<description><![CDATA[Aldec has created interactive VHDL and Verilog learning tools that have been used by thousands of engineers and students to quickly get familiar with HDL design concepts and languages&#8217; syntax. The Evita™ Tutorial is structured in the same way as traditional book: it is composed of chapters, sections and pages. Also, like in the books [...]<img alt="" border="0" src="http://stats.wordpress.com/b.gif?host=utnvhdl.wordpress.com&amp;blog=1756929&amp;post=13&amp;subd=utnvhdl&amp;ref=&amp;feed=1" width="1" height="1" />]]></description>
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		<slash:comments>0</slash:comments>
	
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			<media:title type="html">Rodrigo G.</media:title>
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		<item>
		<title>Core 3DES / DES (VHDL) en OpenCores.org</title>
		<link>http://utnvhdl.wordpress.com/2008/03/06/core-3des-des-vhdl-en-opencoresorg/</link>
		<comments>http://utnvhdl.wordpress.com/2008/03/06/core-3des-des-vhdl-en-opencoresorg/#comments</comments>
		<pubDate>Thu, 06 Mar 2008 14:02:24 +0000</pubDate>
		<dc:creator>Rodrigo G.</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[I+D]]></category>
		<category><![CDATA[VHDL]]></category>

		<guid isPermaLink="false">http://utnvhdl.wordpress.com/?p=12</guid>
		<description><![CDATA[This is a VHDL implementation of Triple-DES (pipelined) and DES cryptographic algorithms, as recommended by NIST. More details: http://www.opencores.org/projects.cgi/web/3des_vhdl/overview<img alt="" border="0" src="http://stats.wordpress.com/b.gif?host=utnvhdl.wordpress.com&amp;blog=1756929&amp;post=12&amp;subd=utnvhdl&amp;ref=&amp;feed=1" width="1" height="1" />]]></description>
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		<slash:comments>0</slash:comments>
	
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			<media:title type="html">Rodrigo G.</media:title>
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		<item>
		<title>Petalinux</title>
		<link>http://utnvhdl.wordpress.com/2008/02/29/petalinux/</link>
		<comments>http://utnvhdl.wordpress.com/2008/02/29/petalinux/#comments</comments>
		<pubDate>Fri, 29 Feb 2008 14:49:00 +0000</pubDate>
		<dc:creator>Rodrigo G.</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[I+D]]></category>
		<category><![CDATA[VHDL]]></category>

		<guid isPermaLink="false">http://utnvhdl.wordpress.com/2008/02/29/petalinux/</guid>
		<description><![CDATA[PetaLinux is source-based hardware and software distribution which has been developed specifically for using Embedded Linux on reconfigurable logic devices. The PetaLinux distribution includes everything needed to easily create Linux systems running on Xilinx field programmable gate arrays (FPGAs). PetaLinux is developed and maintained by PetaLogix. PetaLinux builds upon and extends the well-known uClinux-dist build [...]<img alt="" border="0" src="http://stats.wordpress.com/b.gif?host=utnvhdl.wordpress.com&amp;blog=1756929&amp;post=11&amp;subd=utnvhdl&amp;ref=&amp;feed=1" width="1" height="1" />]]></description>
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		<slash:comments>0</slash:comments>
	
		<media:content url="http://1.gravatar.com/avatar/5b8ab129c6d9c789a2ac4e0e8e68c18a?s=96&#38;d=identicon" medium="image">
			<media:title type="html">Rodrigo G.</media:title>
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		<item>
		<title>How to design with FPGAs from the ground up</title>
		<link>http://utnvhdl.wordpress.com/2007/12/02/how-to-design-with-fpgas-from-the-ground-up/</link>
		<comments>http://utnvhdl.wordpress.com/2007/12/02/how-to-design-with-fpgas-from-the-ground-up/#comments</comments>
		<pubDate>Sun, 02 Dec 2007 15:01:34 +0000</pubDate>
		<dc:creator>rodralez</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[I+D]]></category>

		<guid isPermaLink="false">http://utnvhdl.wordpress.com/2007/12/02/how-to-design-with-fpgas-from-the-ground-up/</guid>
		<description><![CDATA[Step by step tutorial on learning how to design with FPGAs making a &#8220;real-world&#8221; project. http://svenand.blogdrive.com/archive/11.html<img alt="" border="0" src="http://stats.wordpress.com/b.gif?host=utnvhdl.wordpress.com&amp;blog=1756929&amp;post=10&amp;subd=utnvhdl&amp;ref=&amp;feed=1" width="1" height="1" />]]></description>
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		<slash:comments>0</slash:comments>
	
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			<media:title type="html">rodralez</media:title>
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		<item>
		<title>Docs para introducción de uCLinux para Microblaze</title>
		<link>http://utnvhdl.wordpress.com/2007/11/07/docs-para-introduccion-de-uclinux-para-microblaze/</link>
		<comments>http://utnvhdl.wordpress.com/2007/11/07/docs-para-introduccion-de-uclinux-para-microblaze/#comments</comments>
		<pubDate>Wed, 07 Nov 2007 23:45:31 +0000</pubDate>
		<dc:creator>rodralez</dc:creator>
				<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://utnvhdl.wordpress.com/2007/11/07/docs-para-introduccion-de-uclinux-para-microblaze/</guid>
		<description><![CDATA[XAPP730 Getting Started with uClinux on the MicroBlaze Processor Creating a Simple Clinux ready MicroBlaze Design<img alt="" border="0" src="http://stats.wordpress.com/b.gif?host=utnvhdl.wordpress.com&amp;blog=1756929&amp;post=9&amp;subd=utnvhdl&amp;ref=&amp;feed=1" width="1" height="1" />]]></description>
		<wfw:commentRss>http://utnvhdl.wordpress.com/2007/11/07/docs-para-introduccion-de-uclinux-para-microblaze/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
	
		<media:content url="http://0.gravatar.com/avatar/645e3094005c8ab3353c7840c208aa4f?s=96&#38;d=identicon" medium="image">
			<media:title type="html">rodralez</media:title>
		</media:content>
	</item>
		<item>
		<title>time constraints</title>
		<link>http://utnvhdl.wordpress.com/2007/11/07/time-constraints-2/</link>
		<comments>http://utnvhdl.wordpress.com/2007/11/07/time-constraints-2/#comments</comments>
		<pubDate>Wed, 07 Nov 2007 23:39:51 +0000</pubDate>
		<dc:creator>flavianil</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[VHDL]]></category>

		<guid isPermaLink="false">http://utnvhdl.wordpress.com/2007/11/07/time-constraints-2/</guid>
		<description><![CDATA[rodri, fijat si podes averiguar lo de las restricciones de tiempo xq no lo he podido hacer andar. Lo maximo que permite el ice el 1 ms pero de todas formas no funciona. Hasta ahora el mejor metodo sigue siendo el contador.<img alt="" border="0" src="http://stats.wordpress.com/b.gif?host=utnvhdl.wordpress.com&amp;blog=1756929&amp;post=8&amp;subd=utnvhdl&amp;ref=&amp;feed=1" width="1" height="1" />]]></description>
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		<slash:comments>0</slash:comments>
	
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			<media:title type="html">flavianil</media:title>
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	</item>
		<item>
		<title>Picoblaze start</title>
		<link>http://utnvhdl.wordpress.com/2007/10/02/picoblaze-start/</link>
		<comments>http://utnvhdl.wordpress.com/2007/10/02/picoblaze-start/#comments</comments>
		<pubDate>Tue, 02 Oct 2007 14:48:46 +0000</pubDate>
		<dc:creator>Rodrigo G.</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[I+D]]></category>
		<category><![CDATA[VHDL]]></category>

		<guid isPermaLink="false">http://utnvhdl.wordpress.com/2007/10/02/picoblaze-start/</guid>
		<description><![CDATA[Si se tiene un kit de desarrollo de Diligent basado en una FPGA Spartan, hay una nota de aplicación de Xilinx que explica como usar el display de LCD que trae dicho kit, cuyo uso está implementado usando Picoblaze. Este documento está bueno como para empezar a jugar un poco con esta tecnología y entender [...]<img alt="" border="0" src="http://stats.wordpress.com/b.gif?host=utnvhdl.wordpress.com&amp;blog=1756929&amp;post=6&amp;subd=utnvhdl&amp;ref=&amp;feed=1" width="1" height="1" />]]></description>
		<wfw:commentRss>http://utnvhdl.wordpress.com/2007/10/02/picoblaze-start/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
	
		<media:content url="http://1.gravatar.com/avatar/5b8ab129c6d9c789a2ac4e0e8e68c18a?s=96&#38;d=identicon" medium="image">
			<media:title type="html">Rodrigo G.</media:title>
		</media:content>
	</item>
		<item>
		<title>Pedido de más kits a Xilinx</title>
		<link>http://utnvhdl.wordpress.com/2007/09/26/pedido-de-mas-kits-a-xilinx/</link>
		<comments>http://utnvhdl.wordpress.com/2007/09/26/pedido-de-mas-kits-a-xilinx/#comments</comments>
		<pubDate>Wed, 26 Sep 2007 17:28:18 +0000</pubDate>
		<dc:creator>rodralez</dc:creator>
				<category><![CDATA[FPGA]]></category>

		<guid isPermaLink="false">http://utnvhdl.wordpress.com/2007/09/26/pedido-de-mas-kits-a-xilinx/</guid>
		<description><![CDATA[Gente, me contestaron de Xilinx que no nos pueden volver a donar otros kits debido a &#8220;budgetary constraints&#8221;, así que habrá que empezar a ahorrar<img alt="" border="0" src="http://stats.wordpress.com/b.gif?host=utnvhdl.wordpress.com&amp;blog=1756929&amp;post=5&amp;subd=utnvhdl&amp;ref=&amp;feed=1" width="1" height="1" />]]></description>
		<wfw:commentRss>http://utnvhdl.wordpress.com/2007/09/26/pedido-de-mas-kits-a-xilinx/feed/</wfw:commentRss>
		<slash:comments>2</slash:comments>
	
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			<media:title type="html">rodralez</media:title>
		</media:content>
	</item>
		<item>
		<title>Hello world!</title>
		<link>http://utnvhdl.wordpress.com/2007/09/20/hello-world/</link>
		<comments>http://utnvhdl.wordpress.com/2007/09/20/hello-world/#comments</comments>
		<pubDate>Thu, 20 Sep 2007 13:04:00 +0000</pubDate>
		<dc:creator>rodralez</dc:creator>
				<category><![CDATA[Miceláneos]]></category>

		<guid isPermaLink="false"></guid>
		<description><![CDATA[Posteo de prueba<img alt="" border="0" src="http://stats.wordpress.com/b.gif?host=utnvhdl.wordpress.com&amp;blog=1756929&amp;post=1&amp;subd=utnvhdl&amp;ref=&amp;feed=1" width="1" height="1" />]]></description>
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		<slash:comments>2</slash:comments>
	
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			<media:title type="html">rodralez</media:title>
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